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Affiliates – Ahmedullah Aziz

Prof. Ahmedullah Aziz

[email protected]

Assistant Professor, Department of Electrical Engineering and Computer Science, University of Tennessee Knoxville

Research focus: Quantum Materials, e.g. synthesis, molecular quantum systems, 2D materials, quantum magnetism, strongly correlated electron systems, Quantum Theory and Simulations, e.g. AI, high performance computing, topology, algorithmic development, correlated systems, Quantum Information and Communications, Quantum Control and Measurement, e.g. spectroscopy, out of equilibrium quantum measurement and sensing, transport, and devices

Website https://nordic.eecs.utk.edu/

Follow on https://www.linkedin.com/in/ahmedullahaziz/

Bio

Ahmedullah Aziz is an Assistant Professor of Electrical Engineering & Computer Science at the University of Tennessee, Knoxville, USA. He earned his Ph.D. in Electrical & Computer Engineering from Purdue University in 2019, an MS degree in Electrical Engineering from the Pennsylvania State University(University Park) in 2016, and a BS degree in Electrical & Electronic Engineering from Bangladesh University of Engineering & Technology (BUET) in 2013. Before beginning his graduate studies, Dr. Aziz worked in the Samsung R&D Institute in Bangladesh as a full-time Engineer. During graduate education, he worked as a Co-Op Engineer (Intern) in the Technology Research division of Global Foundries (Fab 8, NY, USA). He received several accolades for his research, including the ‘ACM SIGDA Outstanding Ph.D. Dissertation Award (2021)’ from the Association of Computing Machinery, ‘EDAA Outstanding Ph.D. Dissertation Award (2020)’ from the European Design and Automation Association, ‘Outstanding Graduate Student Research Award (2019)’ from the College of Engineering, Purdue University, and ‘Icon’ award from Samsung (2013). He was a co-recipient of two best publication awards (2015, 2016) from the SRC-DARPA STARnet Center. He is a technical program committee (TPC) member for multiple flagship conferences (including DAC, ISCAS, GLSVLSI, Nano), a reviewer for several journals from reputed publishers (IEEE, AIP, Elsevier, Frontiers, IOP Science, Springer Nature), and a review panelist for the US Department of Energy (DOE). He serves as an editorial board member for multiple journals including – ‘Scientific Reports’, and ‘Frontiers in Nanotechnology’.

Research Description

My group specialize in physics-based/phenomenological modeling of quantum devices. We also work on cryogenic/superconducting electronics. We explore electronics applications of emerging quantum phenomena.

Recent research

1. https://aip.scitation.org/doi/abs/10.1063/5.0060716

2. https://www.nature.com/articles/s41598-021-87056-7

3. https://aip.scitation.org/doi/abs/10.1063/5.0092169

4. https://ieeexplore.ieee.org/abstract/document/9116823

5. https://ieeexplore.ieee.org/abstract/document/9855813

6. https://ieeexplore.ieee.org/abstract/document/9855804

7. https://ieeexplore.ieee.org/abstract/document/9928634

8. https://arxiv.org/abs/2210.03874

9. https://arxiv.org/abs/2111.09436

10. https://arxiv.org/abs/2204.07503

Research Image

The interplay between ferromagnetism and topological properties of electronic band structures leads to a precise quantization of Hall resistance without any external magnetic field. This so-called quantum anomalous Hall effect (QAHE) is born out of topological correlations and is oblivious to low-sample quality. It was envisioned to lead toward dissipation-less and topologically protected electronics. We constructed an ultra-low power, non-volatile, cryogenic memory architecture leveraging the QAHE phenomenon in moiré graphene heterostructure. We perform the memory write operation through controlled hysteretic switching between the quantized Hall states, using nano-ampere level currents with opposite polarities. The non-destructive read operation is performed by sensing the polarity of the transverse Hall voltage using a separate pair of terminals. We custom-designed the memory architecture with a novel sensing mechanism to avoid accidental data corruption, ensure the highest memory density and minimize array leakage power. Our design provides a pathway toward realizing topologically protected memory devices.

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